March 1999 SDRAM Comparison

Try this little experiment, take a normally sharpened pencil, and using a straight edge draw a vertical line. Moving the straight edge a millimeter or so to the left draw another line parallel to the first one, now take a look at what you've done. You have two lines, however the lines aren't completely independent of one another, provided your pencil wasn't razor sharp the lines probably started to blend into each other somewhat in between the two.

The same thing applies to SDRAM, the PC100 specification includes explicit details as to the width and spacing of trace lines (the lines printed on PCB's) in order to minimize the levels of cross talk (electrical interference, on the experiment above it would be the points where the two lines blended into each other) between traces adjacent or parallel to one another. The SDRAM modules out on the market today don't follow any set specification for trace length and width, some manufacturers chose to use specifications much like those described in the PC100 specification, while others are far from that.

There are two more parts to the PC100 specification that must be mentioned in order to get the main idea of the purpose of the specification, the first is the Detailed SDRAM component specification. This basically states that a manufacturer MUST use PC100 compliant SDRAMs (the actual chips) in order for their modules, which also must meet the PC100 specification, in order for them to market their modules as PC100 compliant SDRAM. The chips used on PC100 compliant SDRAM modules must be manufactured using a special die and must have an access time of around 8ns.

Finally, the PC100 specification provides a detailed description of the timing parameters and data to be included on the onboard Serial Presence Detect (SPD) EEPROM located on ALL PC100 SDRAM modules. This SPD EEPROM is used to communicate with the motherboard's chipset (e.g. 440BX, 440ZX), and although it won't really make a difference with Aladdin V, MVP3, and SiS 5591 motherboards, it allows the BIOS and the Chipset to communicate with the memory to properly configure the memory timings to control the memory. Without a properly programmed EEPROM the BX chipset may misinterpret an instruction or the BIOS may "guess" as to how the SDRAM should be configured, in both cases resulting in unstable system operation.

Although some manufacturers did submit "PC133" compliant SDRAM modules, the specification has yet to be released from Intel, and all modules claiming to be "PC133 compliant" are actually good guesses at what the specification will call for. Chances are that once the true PC133 modules hit the market, the bar of stability will be raised once again, however until then, don't fall for any manufacturers claiming to have PC133 modules already available. In fact, AnandTech's showed that the preliminary PC133 samples didn't even outperform some of the standard PC100 modules in terms of stability.

In time, with the push from Intel and AMD to push the limits of the standard FSB frequency to 133MHz and beyond, the PC133 specification should become a reality, however until Intel officially announces anything, there is no PC133 compliance officially in existence. Without an official specification, what may be the specification today may be different from what the specification states a week from now. All manufacturers are doing now is guessing at what the final specification will be and are hoping to get a head start on the competition by having PC133 compliant modules ready and waiting at the release of the specification.

As you've probably already learned, in the computer hardware industry, patience is one of your greatest virtues, don't jump the gun too quickly with PC133. Let the manufacturers sort themselves out, then make your move.